🤖 AI Summary
Accurately identifying computational, memory bandwidth, and memory latency bottlenecks—and quantifying associated resource slack—is critical yet challenging for HPC application performance tuning. This paper introduces the first model-agnostic, instruction-level precise noise-injection framework for bottleneck analysis. Leveraging the LLVM toolchain, it selectively injects computational or memory-access noise instructions to decouple the impact of each resource constraint, enabling fine-grained bottleneck classification and quantitative slack measurement. Unlike prior approaches, it requires no hardware modeling assumptions and is portable across diverse architectures. Evaluated on heterogeneous memory systems—including HBM and DDR—it demonstrates robust effectiveness. The method significantly improves the precision of optimization decisions and hardware selection guidance, addressing key limitations of existing tools in slack quantification and root-cause attribution of performance bottlenecks.
📝 Abstract
Bottleneck evaluation plays a crucial part in performance tuning of HPC applications, as it directly influences the search for optimizations and the selection of the best hardware for a given code. In this paper, we introduce a new model-agnostic, instruction-accurate framework for bottleneck analysis based on performance noise injection. This method provides a precise analysis that complements existing techniques, particularly in quantifying unused resource slack. Specifically, we classify programs based on whether they are limited by computation, data access bandwidth, or latency by injecting additional noise instructions that target specific bottleneck sources. Our approach is built on the LLVM compiler toolchain, ensuring easy portability across different architectures and microarchitectures which constitutes an improvement over many state-of-the-art tools. We validate our framework on a range of hardware benchmarks and kernels, including a detailedstudy of a sparse-matrix--vector product (SPMXV) kernel, where we successfully detect distinct performance regimes. These insights further inform hardware selection, as demonstrated by our comparative evaluation between HBM and DDR memory systems.