🤖 AI Summary
This study addresses the challenge of evaluating fault tolerance in digital circuits under failure modes such as missing or misaligned logic gates. The authors propose a novel numerical approach based on generative adversarial networks (GANs), introducing for the first time a GAN architecture that employs complex-valued representations. This framework generates bit-level current configurations corresponding to ideal circuit behavior and compares them against actual signal responses to quantify output deviations, enabling fine-grained fault tolerance analysis. Experimental results demonstrate that the method effectively distinguishes and precisely measures the impact of various fault types on circuit outputs, significantly enhancing both the efficiency and accuracy of robustness assessment in electronic design.
📝 Abstract
We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the realistic signals of a numerical experiment at the discriminator part of the Generative Adversarial Network (GAN) to calculate the deviation from ideal digital electronic signals, including various error modes, such as missing or interchanged logical devices. From the present analysis of a representation of the GAN in terms of complex variables, it is possible to evaluate the robustness in electronic designs by differentiating the impact of failure modes associated with different classical logical elements in the circuit.