🤖 AI Summary
Silicon photonic integrated circuits lack systematic design-for-testability methodologies, making it challenging to efficiently detect manufacturing variations and functional faults. This work introduces, for the first time, a design-for-testability framework tailored to this domain, proposing a generic test architecture that leverages dedicated test access and fault-detection circuitry to achieve high-coverage validation of optical signal power and phase. The approach accommodates complex topologies, including those with feedback loops, and is co-designed with silicon photonic device modeling, electromagnetic simulation, and manufacturing variation analysis. Simulation results on feedforward photonic neural networks and feedback-based photonic logic circuits demonstrate that the proposed architecture effectively identifies photonic signal anomalies, significantly enhancing functional verification capability.
📝 Abstract
This paper proposes a design-for-test (DFT) methodology and architecture for testing and validation of silicon photonic integrated circuits. We describe the design of silicon photonic circuits and components that comprise the proposed DFT architecture. The designs are extensively simulated and validated as test-access and fault-detection circuitry. We demonstrate how the DFT approach can be deployed on photonic integrated circuits and how they can be tested for correct operation, in terms of signal power and phase. The application is demonstrated on two distinct types of designs -- an optical neural network comprising optical devices in a feed-forward topology, and on an optical logic circuit with feedback loops.