π€ AI Summary
DRAM scaling has exacerbated RowHammer attacks, and existing defenses struggle to mitigate sophisticated multi-bank hammering patterns. This work proposes a lightweight reinforcement learningβbased throttling mechanism that dynamically adjusts per-core memory throughput via online Q-learning within the memory controller, requiring neither DRAM hardware modifications nor offline training. By employing per-core, per-bank FIFO queues and compact Q-tables implemented in SRAM, the system detects and suppresses anomalous access patterns in real time within each t_REFW window. Experimental results demonstrate that the proposed approach completely eliminates bit flips when N_BO = 64 and reduces them by up to 22,000Γ when N_BO = 20, while achieving performance improvements of up to 73.6% over the state-of-the-art defense schemes.
π Abstract
RowHammer vulnerability continues to intensify with DRAM scaling, reducing the activation threshold needed to induce bitflips and rendering existing defenses such as TRR, ECC, and refresh-based mechanisms vulnerable to sophisticated multi-bank hammering patterns. This work presents ARTA, a lightweight reinforcement-learning-based throttling mechanism that detects and suppresses RowHammer activity by monitoring fine-grained memory access behavior within the DRAM refresh window (t_REFW) and dynamically adjusting core throughput using a Q-learning frequency scaling governor. ARTA requires no DRAM-side hardware modification or offline training, using small SRAM structures in the memory controller -- a per-core, per-bank FIFO queue (CBF) and a compact Q-table -- for immediate deployment. Our evaluation shows that ARTA eliminates all bitflips at N_BO values down to 64, reduces bitflips up to 22K times at N_BO of 20, and improves performance up to 73.6% over state-of-the-art mitigation mechanisms by limiting preventive action overheads for improved memory bandwidth throughput. These results demonstrate that adaptive RL-based throttling provides robust, scalable, and high-performance RowHammer mitigation for emerging DRAM systems.