Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA

2026-06-09

AI Summary

This work addresses the vast and complex design space of FPGA accelerators, which traditionally relies heavily on manual tuning. It introduces, for the first time, retrieval-augmented generation (RAG) and chain-of-thought (CoT) prompting into the SECDA framework, establishing an automated design space exploration methodology that integrates structured exploration, large language model (LLM) reasoning, and closed-loop feedback. By synergistically combining SystemC simulation, FPGA execution, and iterative reinforcement-based optimization, the approach enables adaptive architectural configuration across diverse AI workloads. Evaluated on three representative operators—vector multiplication, 2D convolution, and matrix transpose—the method achieves end-to-end deployment, effectively balancing computational parallelism and data movement, substantially reducing manual intervention, and significantly accelerating the exploration process.

Abstract

Designing FPGA-based accelerators for modern artificial intelligence workloads requires exploring a large and complex hardware design space that involves architectural parameters, data flow strategies, and memory hierarchies, making the process very time consuming. While existing methodologies such as SECDA enable rapid hardware-software co-design through SystemC simulation and FPGA execution, identifying efficient accelerator configurations remains a largely manual process requiring extensive domain knowledge. SECDA-DSE is a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem to guide design space exploration (DSE) of FPGA-based accelerators. It combines a structured DSE Explorer for generating candidate architectures with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, coupled with a feedback loop for iterative and reinforced refinement. Building on our previous work introducing SECDA-DSE, this paper extends its evaluation by generating three accelerator designs, including element-wise vector multiplication, 2D convolution, and matrix transpose, and performing end-to-end execution on FPGA hardware. The results show that SECDA-DSE can generate SECDA-compliant accelerator designs that are successfully synthesized and executed on FPGA hardware. Furthermore, the generated designs capture kernel-specific trade-offs between compute parallelism and data movement, highlighting the potential of LLM-guided exploration to adapt architectural configurations across diverse workloads while reducing exploration time and the need for extensive human expertise.

Problem

• FPGA accelerator
• design space exploration
• autonomous design
• hardware-software co-design
• AI workloads

Innovation

• LLM-guided design
• FPGA accelerator
• design space exploration
• retrieval-augmented generation
• hardware-software co-design