TransPlace: Transferable Circuit Global Placement via Graph Neural Network

2025-01-10

AI Summary

To address efficiency and quality bottlenecks in very-large-scale integration (VLSI) global placement caused by ever-increasing circuit scale, this work proposes the first end-to-end continuous-space placement method enabling cross-circuit knowledge transfer. Our approach constructs a netlist graph model, incorporates SE(2)-invariant positional encodings, designs a customized graph neural network (GNN), and adopts a coarse-to-fine two-stage optimization strategy—breaking from conventional per-circuit retraining paradigms. Trained on only a small set of high-quality layouts, the model generalizes effectively to unseen million-gate mixed-size-cell circuits: achieving 1.2× speedup in placement runtime, 5% wirelength reduction, 30% congestion reduction, and 9% timing improvement. The core contribution is the first realization of geometry-invariant representation-driven cross-design knowledge transfer, significantly enhancing scalability and generalization capability of learning-based VLSI placement.

Technology Category

• Computer Vision: Representation Learning for Vision
• Search and Optimization: Learning to Search
• Planning, Routing, and Scheduling: Planning/Scheduling and Learning

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking

Abstract

Global placement, a critical step in designing the physical layout of computer chips, is essential to optimize chip performance. Prior global placement methods optimize each circuit design individually from scratch. Their neglect of transferable knowledge limits solution efficiency and chip performance as circuit complexity drastically increases. This study presents TransPlace, a global placement framework that learns to place millions of mixed-size cells in continuous space. TransPlace introduces i) Netlist Graph to efficiently model netlist topology, ii) Cell-flow and relative position encoding to learn SE(2)-invariant representation, iii) a tailored graph neural network architecture for informed parameterization of placement knowledge, and iv) a two-stage strategy for coarse-to-fine placement. Compared to state-of-the-art placement methods, TransPlace-trained on a few high-quality placements-can place unseen circuits with 1.2x speedup while reducing congestion by 30%, timing by 9%, and wirelength by 5%.

Problem

• Circuit Global Routing
• Efficiency Optimization
• Chip Performance

Innovation

• Graph Neural Networks
• Circuit Global Placement
• Coarse-to-Fine Strategy