🤖 AI Summary
This work addresses the scalability and ion transport efficiency limitations of one-dimensional linear ion traps, which hinder the execution of large-scale quantum algorithms. The authors propose a two-dimensional segmented ion trap architecture based on quantum charge-coupled device (QCCD) principles, incorporating T-junctions and a fine-grained shuttling cost model that assigns distinct cost functions to operations on linear segments and junctions. They further develop a task-oriented co-compilation strategy that jointly optimizes architecture mapping and algorithm compilation. By adopting a modular chip layout, the approach significantly reduces transport overhead for representative quantum circuits such as the quantum Fourier transform and adders. Experimental results demonstrate that, under identical shuttling cost assumptions, the two-dimensional architecture outperforms its one-dimensional counterpart, with the performance advantage growing as the number of qubits increases, thereby confirming its superior scalability and efficiency.
📝 Abstract
Shuttle-based trapped ion quantum processors typically employ a one-dimensional (1D) linear architecture to transport ion-qubits between one ore more laser interaction zones where the quantum gates are implemented, along with several qubit register storage segments. The two-dimensional (2D) quantum CCD architecture employs also T- or X-junctions for an improved scaling and efficiency. Here, we explore the shuttling layer in the compilation of quantum algorithm typical building blocks in such architecture. To weight the effort of linear shuttle and junction shuttle, we introduce individual cost functions for each operation. This allows comparing the total cost for quantum circuit building blocks such as the QFT, Carry, Adder, Shift, and Comparator circuits. We study their scaling properties with increased qubit numbers. At equivalent transport cost for junction and linear shuttling, we show that 2D architectures outperform the 1D linear trap with the ratio improving as the number of ions increases. Finally, we discuss the use of cells, such that the entire processor is constructed from a 2D array of such interconnected cells. The work aims to optimize quantum processor architectures, implementing a co-design that fits to the specific task and scaling up in a shuttle-efficient way.