🤖 AI Summary
To address the von Neumann bottleneck—characterized by excessive data movement and low energy efficiency—in LPN-based post-quantum cryptographic schemes under large-table scenarios, this work proposes an RRAM-based in-memory computing accelerator. Methodologically, it introduces a folded current-amplification circuit to suppress leakage current from high-resistance states; designs an accumulate-XOR encoding scheme enabling efficient analog-domain implementation of the joint AND/XOR operations essential for LPN; and employs low-precision approximate computing to reduce hardware overhead. Experimental results demonstrate >99.7% accuracy for AND operations, energy efficiency reaching the TOPS/W level, and a two-order-of-magnitude improvement over GPU-based implementations. The accelerator significantly enhances both computational throughput and energy efficiency for LPN evaluation.
📝 Abstract
As a strong candidate for the post-quantum crypto-graphic (PQC) era, Learning Parity with Noise (LPN) has been extensively studied in the field of cryptography. However, the data transfer bottleneck between the computation and memory modules has significantly hindered the development of LPN-based cryptographic techniques due to large matrices. This work introduces an RRAM-based in-memory computing LPN accelerator aimed at overcoming data transfer bottlenecks, thereby executing LPN computation tasks efficiently. To ensure the high accuracy of the LPN AND operation, a folded current amplification circuit is proposed to address the leakage current issue caused by the limited high-resistance state of RRAM. Meanwhile, a Cumulative XOR Fast Computing Method is introduced to efficiently convert accumulated current values into LPN XOR operation results.