A Fully Pipelined FIFO Based Polynomial Multiplication Hardware Architecture Based On Number Theoretic Transform

2025-01-21

AI Summary

To address the high computational overhead and substantial hardware resource consumption of polynomial multiplication in post-quantum cryptographic schemes such as Ring-LWE (RLWE), this paper proposes a fully pipelined FPGA hardware architecture based on the Number Theoretic Transform (NTT). We innovatively design a fully pipelined FIFO structure that enables n-degree polynomial multiplication in only n/2 clock cycles—reducing latency by 50% and doubling throughput compared to the state-of-the-art. Furthermore, through parallel computation and optimized memory access, the architecture significantly reduces LUT and BRAM utilization. The resulting design achieves an optimal trade-off among high throughput, low latency, and minimal resource consumption, providing an efficient and scalable hardware acceleration solution for RLWE-based encryption.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Natural Language Processing: Learning & Optimization for NLP

Application Category

• Security and Privacy: Applications of cryptography
• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

This paper presents digital hardware for computing polynomial multiplication using Number Theoretic Transform (NTT), specifically designed for implementation on Field Programmable Gate Arrays (FPGAs). Multiplying two large polynomials applies to many modern encryption schemes, including those based on Ring Learning with Error (RLWE). The proposed design uses First In, First Out (FIFO) buffers to make the design fully pipelined and capable of computing two n degree polynomials in n/2 clock cycles. This hardware proposes a two-fold reduction in the processing time of polynomial multiplication compared to state-of-the-art enabling twice as much encryption in the same amount of time. Despite that, the proposed hardware utilizes fewer resources than the fastest-reported work.

Problem

• Polynomial Multiplication
• Cryptography Acceleration
• Resource Optimization

Innovation

• NTT-based Polynomial Multiplication
• FPGA Implementation
• High-speed Cryptographic Processing