Learning to Optimize Capacity Planning in Semiconductor Manufacturing

2025-09-19

AI Summary

Semiconductor manufacturing faces challenges in capacity planning under dynamic demand, where conventional heuristic rules fail to model complex interactions among equipment and processes or predict emerging bottlenecks. Method: This paper proposes a deep reinforcement learning (DRL) framework integrating a heterogeneous graph neural network (HGNN), the first such application to manufacturing capacity planning. The HGNN explicitly models multi-type entities—equipment, operations, and products—and their heterogeneous relationships, enabling fine-grained resource scheduling and proactive bottleneck identification. A scalable policy training technique is further adopted to handle large-scale, machine-level action spaces efficiently. Contribution/Results: Evaluated on Intel’s Minifab simulation model and the SMT2020 benchmark platform, the method achieves up to 1.8% higher throughput and 1.8% shorter cycle time in the largest scenario, significantly surpassing the dynamic optimization capability of traditional heuristics.

Technology Category

• Planning, Routing, and Scheduling: Learning for Planning and Scheduling
• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

In manufacturing, capacity planning is the process of allocating production resources in accordance with variable demand. The current industry practice in semiconductor manufacturing typically applies heuristic rules to prioritize actions, such as future change lists that account for incoming machine and recipe dedications. However, while offering interpretability, heuristics cannot easily account for the complex interactions along the process flow that can gradually lead to the formation of bottlenecks. Here, we present a neural network-based model for capacity planning on the level of individual machines, trained using deep reinforcement learning. By representing the policy using a heterogeneous graph neural network, the model directly captures the diverse relationships among machines and processing steps, allowing for proactive decision-making. We describe several measures taken to achieve sufficient scalability to tackle the vast space of possible machine-level actions. Our evaluation results cover Intel's small-scale Minifab model and preliminary experiments using the popular SMT2020 testbed. In the largest tested scenario, our trained policy increases throughput and decreases cycle time by about 1.8% each.

Problem

• Optimizing semiconductor manufacturing capacity planning with neural networks
• Addressing complex process flow interactions causing production bottlenecks
• Improving throughput and cycle time using machine-level decision-making

Innovation

• Neural network-based model for capacity planning
• Trained using deep reinforcement learning
• Heterogeneous graph neural network captures relationships