Channel-wise Parallelizable Spiking Neuron with Multiplication-free Dynamics and Large Temporal Receptive Fields

2025-01-24

AI Summary

To address the challenges of slow training, high hardware overhead, and poor deployability of Spiking Neural Networks (SNNs) on resource-constrained devices for long-sequence modeling, this paper proposes a hardware-friendly SNN architecture. Our method introduces four key innovations: (1) a channel-wise parallelized dynamic neuron model enabling large temporal receptive fields; (2) channel-wise convolution to enhance spatiotemporal feature extraction; (3) a sawtooth dilation mechanism that reduces computational complexity; and (4) fully shift-based arithmetic operations replacing multiplications, significantly lowering computational cost and power consumption. Evaluated on benchmark neuromorphic datasets—SHD, CIFAR-seq, and DVS-Lip—our approach achieves state-of-the-art accuracy while accelerating training by 2.1–3.8× and reducing memory footprint by 37%–52%. These results demonstrate substantial improvements in both efficiency and hardware deployability.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

Spiking Neural Networks (SNNs) are distinguished from Artificial Neural Networks (ANNs) for their sophisticated neuronal dynamics and sparse binary activations (spikes) inspired by the biological neural system. Traditional neuron models use iterative step-by-step dynamics, resulting in serial computation and slow training speed of SNNs. Recently, parallelizable spiking neuron models have been proposed to fully utilize the massive parallel computing ability of graphics processing units to accelerate the training of SNNs. However, existing parallelizable spiking neuron models involve dense floating operations and can only achieve high long-term dependencies learning ability with a large order at the cost of huge computational and memory costs. To solve the dilemma of performance and costs, we propose the mul-free channel-wise Parallel Spiking Neuron, which is hardware-friendly and suitable for SNNs' resource-restricted application scenarios. The proposed neuron imports the channel-wise convolution to enhance the learning ability, induces the sawtooth dilations to reduce the neuron order, and employs the bit shift operation to avoid multiplications. The algorithm for design and implementation of acceleration methods is discussed meticulously. Our methods are validated in neuromorphic Spiking Heidelberg Digits voices, sequential CIFAR images, and neuromorphic DVS-Lip vision datasets, achieving the best accuracy among SNNs. Training speed results demonstrate the effectiveness of our acceleration methods, providing a practical reference for future research.

Problem

• Spiking Neural Networks
• Long Temporal Sequence
• Computational Efficiency

Innovation

• Non-multiplicative Channel-wise Parallel Spiking Neuron
• resource efficiency
• Spiking Neural Networks (SNNs) acceleration