🤖 AI Summary
Temporal interference arising from shared cache and memory bandwidth among multiple virtual machines (VMs) in mixed-criticality embedded systems undermines timing predictability and system certification. Method: We propose the first configurable, analyzable co-interference mitigation framework. It systematically models and quantifies the coupled effects of cache coloring and memory bandwidth reservation (MBR); employs hardware performance counter (HPC)-driven feedback for configuration optimization; and unifies analysis across multiple shared resources—including IOMMU and interrupt controllers. Contribution/Results: Evaluated on a real multi-core platform, the framework significantly improves worst-case execution time (WCET) predictability and throughput stability. Interference suppression effectiveness increases by 32%, while configuration efficiency improves by 5.8×. The open-source implementation supports industrial-grade deployment in mixed-criticality systems.
📝 Abstract
Modern embedded systems are evolving toward complex, heterogeneous architectures to accommodate increasingly demanding applications. Driven by SWAP-C constraints, this shift has led to consolidating multiple systems onto single hardware platforms. Static Partitioning Hypervisors offer a promising solution to partition hardware resources and provide spatial isolation between critical workloads. However, shared resources like the Last-Level Cache and system bus can introduce temporal interference between virtual machines (VMs), negatively impacting performance and predictability. Over the past decade, academia and industry have developed interference mitigation techniques, such as cache partitioning and memory bandwidth reservation. However, configuring these techniques is complex and time-consuming. Cache partitioning requires balancing cache sections across VMs, while memory bandwidth reservation needs tuning bandwidth budgets and periods. Testing all configurations is impractical and often leads to suboptimal results. Moreover, understanding how these techniques interact is limited, as their combined use can produce compounded or conflicting effects on performance. Static analysis tools estimating worst-case execution times offer guidance for configuring mitigation techniques but often fail to capture the complexity of modern multi-core systems. They typically focus on limited shared resources while neglecting others, such as IOMMUs and interrupt controllers. To address these challenges, we present SP-IMPact, an open-source framework for analyzing and guiding interference mitigation configurations. SP-IMPact supports (i) cache coloring and (ii) memory bandwidth reservation, while evaluating their interactions and cumulative impact. By providing insights on real hardware, SP-IMPact helps optimize configurations for mixed-criticality systems, ensuring performance and predictability.