🤖 AI Summary
In millimeter-wave massive multi-user MIMO systems with highly correlated channels, conventional soft-output detection suffers from degraded bit-error-rate performance, while simultaneously achieving low power consumption and small silicon area remains challenging. To address this, this paper proposes a deep-unfolding detection algorithm based on Gram-domain block coordinate descent (GBCD) and designs a corresponding low-power ASIC architecture. The approach innovatively integrates posterior mean estimation (PME)-based denoising with OFDM subcarrier-level resource reuse, enabling a reconfigurable processing unit array fabricated in 22 nm FD-SOI technology. The chip supports base stations with 128 antennas serving 16 users under QPSK–256-QAM modulation, achieving a peak throughput of 7.1 Gbps, a power consumption of 367 mW, and a core area of only 0.97 mm²—delivering state-of-the-art energy efficiency and area efficiency.
📝 Abstract
We present a 22 nm FD-SOI (fully depleted silicon-on-insulator) application-specific integrated circuit (ASIC) implementation of a novel soft-output Gram-domain block coordinate descent (GBCD) data detector for massive multi-user (MU) multiple-input multiple-output (MIMO) systems. The ASIC simultaneously addresses the high throughput requirements for millimeter wave (mmWave) communication, stringent area and power budget per subcarrier in an orthogonal frequency-division multiplexing (OFDM) system, and error-rate performance challenges posed by realistic mmWave channels. The proposed GBCD algorithm utilizes a posterior mean estimate (PME) denoiser and is optimized using deep unfolding, which results in superior error-rate performance even in scenarios with highly correlated channels or where the number of user equipment (UE) data streams is comparable to the number of basestation (BS) antennas. The fabricated GBCD ASIC supports up to 16 UEs transmitting QPSK to 256-QAM symbols to a 128-antenna BS, and achieves a peak throughput of 7.1 Gbps at 367 mW. The core area is only 0.97 mm$^2$ thanks to a reconfigurable array of processing elements that enables extensive resource sharing. Measurement results demonstrate that the proposed GBCD data-detector ASIC achieves best-in-class throughput and area efficiency.