FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems

2026-07-01

AI Summary

This work addresses the cyclic dependency in conventional 2.5D chip integration between dielet placement and interposer footprint: placement is constrained by a predefined interposer size, yet the optimal size itself depends on the placement outcome, often leading to area inefficiency or infeasible solutions. To resolve this, the authors propose FAPlace, a novel framework that treats the interposer footprint as an optimization output rather than a fixed input. Operating on a sufficiently large canvas, FAPlace employs a footprint-aware, mask-guided sequential placement algorithm and jointly optimizes area, aspect ratio, wirelength, and thermal effects through a unified spatial cost function. The approach yields a single deterministic solution that significantly reduces both interconnect wirelength and interposer area, achieves an aspect ratio close to the ideal value of 1, and maintains excellent thermal performance.

Abstract

The placement of chiplets on a silicon interposer is a pivotal step in 2.5D system integration, yet existing placement approaches typically assume a pre-defined interposer footprint. This creates a circular dependency: the optimal footprint cannot be known without first solving the placement, while the placement itself is constrained by the given dimensions. An undersized interposer may exclude feasible placements, while an oversized one yields unnecessarily sparse solutions. Moreover, even when the footprint area is minimized, few existing approaches explicitly control the interposer's aspect ratio. To jointly address these challenges, we propose FAPlace, a footprint aware mask guided sequential placement framework. FAPlace operates on a sufficiently large canvas, eliminating the circular dependency by allowing the optimal interposer footprint to emerge as an output of the optimization rather than a pre-specified input. At its core is a novel footprint mask that fuses area compactness with an aspect ratio penalty into a unified spatial cost map. Integrated with wirelength and thermal guidance masks, FAPlace delivers holistic multi-physics optimization in a deterministic, single pass process. Experimental results demonstrate that FAPlace reduces wirelength and footprint area while achieving near-unity aspect ratios, without compromising on thermal performance.

Problem

• chiplet placement
• interposer footprint
• 2.5D integration
• aspect ratio
• circular dependency

Innovation

• chiplet placement
• interposer footprint
• aspect ratio optimization
• multi-physics optimization
• 2.5D integration