Latch Based Design for Fast Voltage Droop Response

2025-01-31

AI Summary

To address the latency in dynamic frequency scaling (DFS) response and excessive clock synchronization chain length under supply voltage droop in VLSI chips, this paper proposes a PLL-free, latch-based DFS circuit. Methodologically, it replaces conventional masking flip-flops with a differential-sensor-driven latch-masking structure, thereby reconstructing the timing model and establishing formal correctness guarantees. This redesign reduces the synchronization chain length by 50%. Fabricated in 130 nm CMOS technology (IHP platform), the circuit achieves voltage-droop response within only two clock cycles—significantly outperforming state-of-the-art solutions. Experimental results demonstrate superior trade-offs among real-time responsiveness, silicon area, and power consumption. The proposed architecture establishes a new paradigm for low-latency, fault-tolerant clock generation in modern VLSI systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Distributed Search
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

We present a latch-based and PLL-free design of the voltage droop correction circuit of Lenzen, Fuegger, Kinali, and Wiederhakecite{DroopJournal}. Such a circuit dynamically modifies the clock frequency of a digital clock for VLSI systems. Our circuit responds within two clock cycles and halves the length of the synchroniser chain compared to the previous design. Further, we introduce a differential sensor based design for masking latches as a replacement for masking flip flops that the design of cite{DroopJournal} requires, but leaves unspecified. The use of latches instead of threshold-altered flip flops alters the timing properties of our design and thus the proofs of correctness that accompanied their design require modifications which we present here. This design has been successfully implemented on the IHP 130 nm process technology. The results of the experimental measurements will be discussed in a subsequent publication.

Problem

• Computer Chip Performance
• Voltage Drop
• Clock Frequency Adjustment

Innovation

• Adaptive Clock Frequency
• Enhanced Response Time
• Innovative Component Substitution