π€ AI Summary
To address the scarcity of HDL/EDA expertise, high fine-tuning costs, and challenges in automating multi-agent workflows for RTL design, this paper proposes VeriMaASβthe first RTL code generation framework that deeply integrates formal verification feedback into multi-agent collaboration. VeriMaAS leverages weak supervision signals from HDL tool outputs (e.g., assertion pass/fail reports) to guide task decomposition and iterative refinement across agents, eliminating reliance on large-scale annotated datasets or expensive LLM inference. By combining lightweight training strategies with program synthesis techniques, it achieves efficient few-shot RTL synthesis using only hundreds of samples. Empirical evaluation shows a 5β7% improvement in pass@k over fine-tuned baselines, while reducing supervision cost by an order of magnitude. This significantly enhances the practicality and scalability of automated RTL design workflows.
π Abstract
The rise of agentic AI workflows unlocks novel opportunities for computer systems design and optimization. However, for specialized domains such as program synthesis, the relative scarcity of HDL and proprietary EDA resources online compared to more common programming tasks introduces challenges, often necessitating task-specific fine-tuning, high inference costs, and manually-crafted agent orchestration. In this work, we present VeriMaAS, a multi-agent framework designed to automatically compose agentic workflows for RTL code generation. Our key insight is to integrate formal verification feedback from HDL tools directly into workflow generation, reducing the cost of gradient-based updates or prolonged reasoning traces. Our method improves synthesis performance by 5-7% for pass@k over fine-tuned baselines, while requiring only a few hundred training examples, representing an order-of-magnitude reduction in supervision cost.