AlphaRoute: Large Language Models as Semantic Optimizers for Multi-Objective Routing

📅 2026-07-22
📈 Citations: 0
✨ Influential: 0
📄 PDF
🤖 AI Summary
This work addresses the limitations of static penalty strategies in VLSI global routing, which struggle to adapt to complex congestion topologies and jointly optimize congestion, wirelength, and via count. To overcome these challenges, the paper proposes a dynamic multi-objective optimization framework that reformulates rip-up-and-reroute (R&R) as a dynamic system. The approach integrates SHAP-driven congestion decomposition, 3D Dijkstra maze routing, and an adaptive PathFinder algorithm, and—novelty introduced here—employs a large language model as a semantic policy optimizer to dynamically tune penalty parameters under knowledge graph constraints. Evaluated on the ISPD 2025 benchmarks, the method reduces MEMPOOL overflow by 98.6%, lowers ARIANE overflow to 146,109 (a 29.8× improvement over the state of the art), and achieves a penalty score of 0.0538, significantly outperforming the prior best result of 1.780.
📝 Abstract
Very Large Scale Integration (VLSI) global routing is an NP-hard combinatorial optimization problem requiring signal net assignment across capacity-constrained 3D grids while minimizing congestion, wirelength, and via transitions. Because traditional heuristics rely on static penalty schedules that fail on complex congestion topologies, we present AlphaRoute: a multi-objective adaptive search framework reformulating rip-up and reroute (R&R) into a dynamic optimization system. We introduce SHAP-based overflow decomposition to isolate per-net congestion, driving targeted subgraph extraction via 3D Dijkstra maze routing and an adaptive PathFinder policy. Crucially, AlphaRoute employs Large Language Models (LLMs) as semantic policy optimizers. Bounded by a deterministic knowledge graph, the LLMs interpret congestion metrics to dynamically adjust penalty parameters. Evaluated on ISPD 2025 benchmarks, AlphaRoute reduces overflow by 98.6% on MEMPOOL. On the constrained ARIANE design, we achieve an overflow of 146,109 (a 29.8x reduction in overflow over the state of the art), yielding a penalized score of S_orig = 0.0538 versus the State-of-the-art (SOTA) 1.780. These results demonstrate that superior algorithmic search geometry can overcome the latency of interpreted Python implementations.
Problem

Research questions and friction points this paper is trying to address.

VLSI global routing
multi-objective optimization
congestion minimization
NP-hard combinatorial optimization
rip-up and reroute
Innovation

Methods, ideas, or system contributions that make the work stand out.

Large Language Models
VLSI global routing
multi-objective optimization
SHAP-based decomposition
adaptive search
🔎 Similar Papers
No similar papers found.
💼 Related Jobs
No related jobs found.
K
Kabir Murjani
Department of Electrical Engineering, Institute of Technology, Nirma University, Ahmedabad, India
M
Mishri Bhavsar
Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Ahmedabad, India
M
Manish I. Patel
Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Ahmedabad, India
Jonti Talukdar
Jonti Talukdar
NVIDIA | ASU Center for Semiconductor Microelectronics | Duke University (Ph.D.)
Hardware SecurityFunctional SafetySupply Chain SecurityDesign for TestAI Accelerators