A FeFET Voltage-to-Time Converter with Offset Trim by Programmed Multilevel State in 28-nm CMOS

2026-10-04

AI Summary

This study addresses the offset and gain variations in voltage-to-time converters (VTCs) caused by process, voltage, and temperature fluctuations. A FeFET-based VTC implemented in a 28nm CMOS process is proposed, featuring the first use of the non-volatile multi-level programming states of FeFETs for direct input offset calibration. Combined with a current-limited inverter and capacitor-bank gain control, this approach enables in-situ trimming without external circuitry. Measurement results demonstrate that second-harmonic distortion is reduced to −32.2 dB and integral nonlinearity (INL) is improved to 0.92 LSB. Furthermore, simulations verify that the proposed design supports a sampling rate of 500 MS/s while consuming only 2 μW of power.

Abstract

The offset and gain of voltage-to-time converters (VTCs) in time-domain circuits vary with process, supply, and temperature. This work presents a VTC whose nonvolatile input-referred offset trim is the programmed multilevel state of the ferroelectric field-effect transistor (FeFET) that converts the input. Fabricated in 28-nm CMOS, the 6.07-$\mu$m$^2$ VTC consists of a current-starved inverter with the FeFET and a parallel NMOS leaker in its tail, a capacitor bank, and a following inverter. The programmed state shifts the transfer curve onto the input range, leaving the gain to the capacitor bank and the leaker bias. Measured at 10~MS/s, centered states weaken the second harmonic from $-$12.5~dB in the low-threshold state to $-$32.2~dB and lower the static integral nonlinearity (INL) at 5~bit from 2.42 to 0.92~LSB. Post-layout simulations indicate that the proposed VTC can operate at 500~MS/s, drawing 2.0~$\mu$W from a 0.9-V supply, with nearly unchanged distortion and gain up to 700~MS/s. Across simulated process corners and $\pm$10\,\% supply variation, the input-referred offset is calibrated to within 10~mV and the gain to within 4\,\% of nominal by adjusting the programmed state and leaker bias.

Problem

• Voltage-to-Time Converter
• Offset variation
• Gain variation
• PVT variations
• FeFET

Innovation

• FeFET
• Voltage-to-Time Converter
• Offset Trim
• Multilevel State
• Time-Domain Circuits