An ASIC Design Flow for High-Level Synthesis of Asynchronous Circuits

2026-10-04

AI Summary

This study addresses the lack of industrial-grade EDA support and limited high-level synthesis for asynchronous circuits by implementing automated synthesis from imperative programs to asynchronous hardware based on the AHIR framework. The proposed methodology employs a delay-insensitive controller coupled with a single-rail datapath architecture. Furthermore, it introduces 1-safe Petri net modeling and formally proves the necessary and sufficient conditions for timing constraints, while maintaining full compatibility with standard ASIC toolchains. As an end-to-end demonstration, the AES encryption algorithm is synthesized, and post-layout simulations validate both the functional correctness and performance metrics of the resulting circuit. This work ultimately provides a comprehensive solution for the automated design of asynchronous circuits.

Abstract

Asynchronous circuits have some benefits over their synchronous counterparts, such as lower idle power consumption, potentially lower latency, absence of clock distribution issues, among others. However, industry-scale electronic design automation (EDA) support, particularly for high-level synthesis (HLS) of asynchronous systems from imperative programs, remains limited. We present an approach to synthesize asynchronous circuits from imperative programs using the AHIR HLS framework. The framework models the control path in the form of a restricted form of Petri nets that are 1-safe and live by construction. In this work, we start with this representation in AHIR and generate asynchronous circuits with a delay insensitive controller, a single-rail data path with bundled-data interaction between the controller and the data path that resembles the micropipelines architecture. We formalize the timing constraints required for correct functioning of the generated circuit and show that those constraints are one sided (feasible), necessary and sufficient. We have also developed a static timing analyzer to check that the circuit meets these constraints. Our flow integrates seamlessly with off-the-shelf ASIC toolchains and standard synchronous cell libraries. To demonstrate our approach, we show an end to end implementation of an AES encryption algorithm and use post layout circuit simulation to verify the correctness and estimate the performance of the resultant circuit.

Problem

• Asynchronous circuits
• High-Level Synthesis
• Electronic Design Automation
• ASIC design flow

Innovation

• High-Level Synthesis
• Asynchronous Circuits
• Petri Nets
• Bundled-Data
• Static Timing Analysis