Efficient HQC Implementations on RISC-V: A Cross-Layer Design Space Exploration

2026-10-05

AI Summary

This work addresses the limited design space exploration in existing RISC-V post-quantum cryptography implementations, which struggle to balance performance and resource efficiency. We propose a parameterizable architectural framework for the HQC algorithm that leverages hardware-software co-design, RISC-V instruction set extensions, and FPGA prototyping. This approach enables cross-layer design space exploration encompassing nearly 30,000 configurations across three security levels. Experimental results demonstrate that the identified Pareto-optimal configurations significantly outperform state-of-the-art solutions, achieving up to a 69.6× reduction in latency and a minimum 4.8× decrease in LUT resource consumption.

Abstract

RISC-V-based hardware/software co-design has become an established methodology for implementing post-quantum cryptography (PQC) on embedded devices. Its software programmability, extensible instruction-set architecture, and optional dedicated accelerators create a broad design space that offers the flexibility required for crypto-agility and post-deployment updates. For HQC, a PQC key-encapsulation mechanism selected for standardization, several RISC-V-based implementations have already been published. However, these works explore only a small subset of this design space. We present, to the best of our knowledge, the most comprehensive exploration of RISC-V-based HQC. Our exploration is centered around a new, parametrizable architecture framework on which we characterize 29,920 distinct architectural configurations across all three HQC security levels on FPGA. The Pareto-optimal configurations from this framework outperform the state-of-the-art RISC-V-based HQC implementation, ranging from 4.8x lower LUT utilization at 17% lower latency to 69.6x lower latency at 30% lower LUT utilization, while also requiring up to 10.6x fewer block RAMs.

Problem

• Post-Quantum Cryptography
• HQC
• RISC-V
• Hardware/Software Co-design
• Design Space Exploration

Innovation

• Post-Quantum Cryptography
• RISC-V
• Hardware/Software Co-design
• Design Space Exploration
• HQC