FAPO: Fanout-Aware Post-Mapping Optimization for LUT-Based FPGAs

2026-10-03

AI Summary

This study addresses the limitations of logic depth optimization in FPGA mapping, which fails to eliminate fanout bottlenecks while LUT duplication incurs area overhead. To overcome these issues, this work proposes a mapper-independent post-optimization framework. The method derives necessary conditions for full critical paths and employs a minimum-cut algorithm to determine an optimal LUT duplication scheme with minimal replication. Furthermore, it integrates a greedy strategy to jointly refine sink assignment and LUT cuts, achieving synergistic timing and area optimization under area constraints. Experimental results demonstrate that the proposed approach reduces the Area-Timing Product (ATP) metric by 14.48% on average. Additionally, VPR evaluations indicate that the routed critical path delay is reduced by 7.04% compared to ABC if.

Abstract

Reducing logic depth during FPGA technology mapping does not necessarily eliminate fanout bottlenecks in the resulting LUT networks.Replicating heavily loaded LUTs can alleviate these bottlenecks, but the added copies consume area and may increase upstream loading. We propose FAPO, a mapper-independent post-mapping optimizer that jointly refines sink assignments and LUT cuts under a final-area constraint.Replication, cut switching, and recovery are evaluated by the resulting live LUT count.We derive a necessary all-critical-path condition for delay reduction and obtain minimum-copy proposals by minimum cut within a restricted same-cut family.These proposals complement greedy refinement, with mappings selected by full-network area and timing.Experiments on EPFL benchmarks with three initial mappers achieve geometric-mean reductions of up to 14.48% in fanout-aware area--timing product (ATP) with a 5% final-area allowance.VPR evaluation shows a 7.04% reduction in routed critical-path delay relative to ABC if.

Problem

• FPGA technology mapping
• fanout bottleneck
• post-mapping optimization
• LUT replication
• area-timing tradeoff

Innovation

• Fanout-Aware Optimization
• Post-Mapping Optimization
• LUT Replication
• Cut Switching
• FPGA