Synapse Loss Estimation for the BrainScaleS Wafer-scale Neuromorphic System

2026-10-05

AI Summary

This study addresses the synapse loss problem in the BrainScaleS neuromorphic system caused by constrained hardware connectivity. We propose a novel theoretical framework that integrates probabilistic distributions with the hardware routing architecture, employing probabilistic modeling, mixed-signal circuit analysis, and mapping algorithm simulations to precisely predict both the maximum lossless network scale and the synapse loss rate for dense networks. Validated through theoretical derivation and empirical evaluation, this work fills a critical gap in quantitative analysis within the field. It elucidates the fundamental capability boundaries of the system and exposes inherent limitations in existing mapping algorithms. Consequently, the proposed framework provides essential theoretical tools for parameter optimization, benchmarking, and the design of next-generation neuromorphic hardware.

Abstract

Neuromorphic hardware combines memory (synapses) and computation (neurons) into the same silicon substrate to avoid the von-Neumann bottleneck. This way, neuromorphic computing aims to make computational neuroscience simulations and AI processing faster and more energy-efficient. The common crossbar architecture integrates a synapse matrix (analog, mixed-signal or digital) with a neuron array into a neurosynaptic core, whereas multiple cores are interconnected via a dedicated spike routing network. One of such neuromorphic architecture is the BrainScaleS wafer-scale system which allows the realization of very flexible network architecture, supporting both dense and sparse connectivity by highly configurable neurosynaptic cores. Yet, when network models from computational neuroscience are mapped to the BrainScaleS wafer, synapse loss can occur which means that for some model synapses no hardware synapse is available due to the restricted connectivity of the hardware. In this work we analyze the synapse loss when mapping uniform random networks to BrainScaleS both theoretically and empirically. We first develop a methodology to estimate maximum-sized networks without synapse loss based on probability distributions and the hardware's synapse routing architecture. Next, we adopt the methodology to predict the synapse loss for denser or larger network models. Then, we compare the predictions with results from actual runs of the mapping software: The results show the capabilities and limitations of the BrainScaleS system itself and spot shortcomings of the current mapping algorithms. The developed methodology can be helpful in multiple ways: to find the optimal settings when mapping a given network model to BrainScaleS, to act as a benchmark for the mapping software, and as tool for design space exploration for new hardware.

Problem

• synapse loss
• neuromorphic hardware
• BrainScaleS
• network mapping
• crossbar architecture

Innovation

• Neuromorphic Hardware
• Synapse Loss Estimation
• BrainScaleS
• Network Mapping
• Crossbar Architecture