Beyond No-Good Benders Cuts: Exact Realizability for Discretely Tunable Clock Trees

2026-10-05

AI Summary

This study addresses the realizability mismatch between useful skew scheduling and discretely tunable clock trees. To bridge this gap, it constructs a verifiable scheduler–clock tree interface and introduces an exact cut generation method that transcends conventional No-Good learning. Specifically, discrete voids intractable to linear inequalities are effectively separated through membership checking over finite relative delay sets, arithmetic certificate generation, and tree-specific structural contraction techniques. Experimental results demonstrate that the proposed approach significantly reduces oracle invocation counts and accelerates projection construction. Furthermore, it establishes an overhead upper bound for globally minimal certificates, thereby providing an efficient solution framework for the co-optimization of scheduling and clock trees.

Abstract

Useful-skew schedules can satisfy timing constraints yet remain unrealizable by a fixed clock tree with discrete tuning choices. We formulate this mismatch as exact membership in a finite relative-latency set and develop a checkable feedback interface between the scheduler and the tree model. Arithmetic certificates explain unrealizable targets, while tree-specific contraction reduces the structural size of the exact relations projected onto selected sinks. These relations become realizability cuts that can exclude more candidates than a no-good on the same certificate support, including discrete holes that linear inequalities cannot separate. Controlled experiments confirm fewer oracle calls and faster projection construction. They also expose important limits: globally minimum certificates can cost more than they save, compact arithmetic feedback can fail on non-parity obstructions, and direct monolithic optimization remains faster on the tested additive models. The contribution is an exact, independently verifiable scheduler--tree interface, rather than a claim of universal solver acceleration or physical signoff.

Problem

• clock tree synthesis
• useful skew scheduling
• exact realizability
• discrete tuning
• Benders cuts

Innovation

• Benders cuts
• clock tree synthesis
• exact realizability
• useful skew scheduling
• arithmetic certificates