JFS-CryoMem: A Cryogenic Memory with Voltage-Controlled Superconducting Devices and Femtojoule-Scale Write/Read Energies

2026-09-27

AI Summary

This work addresses the urgent demand for non-volatile, low-thermal-disturbance, and superconductor-compatible memory in scalable cryogenic systems by proposing a novel architecture integrating Josephson junction field-effect transistors (JJFETs) with ferroelectric SQUIDs. The core innovation lies in the first-ever separation of read and write paths, enabling voltage-controlled gating and non-destructive operations while supporting independent optimization of programming and sensing conditions alongside half-select programming. Compact model simulations validate the scalability of this architecture from 4×4 to 16×16 arrays. Furthermore, the study elucidates the energy consumption trade-offs inherent to large-scale arrays and establishes the conditions required for maintaining readout distinguishability.

Abstract

Scalable cryogenic systems require memory that combines nonvolatile storage, selective access, low thermal disturbance, and compatibility with superconducting electronics. We present a cryogenic memory architecture that integrates a voltage-controlled Josephson junction field-effect transistor (JJFET) selector with a ferroelectric superconducting quantum interference device (FeSQUID) storage element, hereafter termed JFS-CryoMem. The JJFET provides gate-controlled cell selection, whereas the FeSQUID stores information in stable remanent-polarization states. JFS-CryoMem features separate read and write path mechanisms that support nondestructive readout and independent optimization of programming and sensing conditions. The architecture is evaluated using experimentally calibrated compact models that reproduce the measured electrical characteristics of both constituent devices. We demonstrate selective programming using a half-bias scheme, nonvolatile state retention, and distinguishable readout in a $4 \times 4$ array while accounting for the selected cell and all unselected parallel branches. We then extend the analysis to arrays up to $16 \times 16$ and examine how array scaling alters current distribution, column-equivalent resistance, readout separation, required bitline current, and read energy. The results reveal the principal sensing and energy tradeoffs associated with larger arrays and identify the operating conditions required to preserve read distinguishability as the array grows. JFS-CryoMem provides a device-to-array framework for cryogenic memory in quantum, high-performance, and space-oriented computing systems.

Problem

• cryogenic memory
• nonvolatile storage
• superconducting electronics
• array scaling
• read distinguishability

Innovation

• Cryogenic memory
• JJFET
• FeSQUID
• Nondestructive readout
• Half-bias scheme