S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM

2026-09-27

AI Summary

This work addresses the high dynamic energy consumption and vulnerability to side-channel attacks in MRAM readout circuits by proposing a circuit-device co-design framework. Specifically, it introduces a unified architecture that integrates memory-level current balancing with sensing-level dynamic power equalization. By combining a 4T-2MTJ balanced bitcell with an adiabatic logic sense amplifier based on STT/SOT-MRAM technology, the proposed approach achieves secure and low-power read operations. Experimental results demonstrate that this scheme reduces energy consumption by 80% compared to conventional designs while completely suppressing key leakage. Consequently, it provides a novel memory solution for IoT systems that simultaneously delivers high energy efficiency and robust security.

Abstract

Magnetoresistive Random Access Memory (MRAM) technologies such as Spin-Transfer Torque (STT-MRAM) and Spin-Orbit Torque assisted (SOT-STT-MRAM) offer nonvolatility and low leakage, making them attractive for IoT systems. However, conventional MRAM read circuits face two fundamental challenges: high dynamic energy consumption and vulnerability to side-channel attacks caused by data-dependent current variations in Magnetic Tunnel Junctions (MTJs). This paper presents a Secured Adiabatic Logic Sense Amplifier (SALSA) that addresses both challenges simultaneously through circuit-device co-design. S-ALSA combines structural current balancing via a 4T-2MTJ bit cell, which eliminates read current asymmetry at the storage level, with dynamic power equalization via adiabatic charge recovery in the sensing circuit. The proposed architecture supports both STT-MRAM and SOT-STT-MRAM. Case studies using 4x4 MRAM macros shows up to 80% energy savings over conventional Pre-Charge Sense Amplifiers (PCSA) across IoT frequencies. Correlation Power Analysis (CPA) attacks on PRESENT-80 encryption confirm complete suppression of key leakage when S-ALSA is combined with a balanced bit cell. This work establishes a unified framework where energy efficiency and hardware security are achieved simultaneously, enabling secure and low-power IoT memory design.

Problem

• MRAM
• dynamic energy consumption
• side-channel attacks
• read circuits
• IoT

Innovation

• Adiabatic Logic
• MRAM
• Side-Channel Attack
• Circuit-Device Co-Design
• Balanced Bit-Cell