Coarse-to-Fine Macro Placement via Evolutionary Search and Critical Macro Tuning

2026-09-28

AI Summary

This study addresses the limitation of existing chip macro placement search methods, which are prone to local optima due to restrictive macro selection mechanisms and coarse grid resolution. To overcome these issues, this work proposes C2FPlace, a framework that enables precise coarse-to-fine macro placement. The method integrates evolutionary search with critical macro fine-tuning, introducing tournament selection and stochastic subgraph reconstruction strategies to transcend grid constraints. Furthermore, a two-stage sampling scheme effectively balances exploration and exploitation. Experimental results demonstrate that C2FPlace reduces half-perimeter wire length (HPWL) by over 17.8% on average across the ISPD2005 benchmarks and achieves the best overall power-performance-area (PPA) ranking on the ICCAD2025 benchmarks.

Abstract

Macro placement is a critical stage in chip physical design that substantially affects downstream implementation quality. Recent search-based methods improve existing layouts through partial reconstruction, but quality-biased or spatially restricted macro selection can limit the diversity of reconstruction proposals, potentially hindering escape from local optima. Moreover, coarse-grid representations restrict placement precision. To address these challenges, we propose C2FPlace, a \textbf{C}oarse-to-\textbf{F}ine macro \textbf{Place}ment framework that integrates population-based evolutionary search with fine-grained refinement. During coarse-grained optimization, tournament selection chooses promising parents from randomly sampled groups of layouts, and stochastic partial rip-up and re-place generates offspring by sampling macro subsets across the entire layout. A two-phase schedule samples reconstruction ratios from a higher range early in the search and a lower range later, supporting broad exploration followed by more conservative refinement. During fine-grained optimization, critical macro tuning enables positional adjustments beyond the coarse grid to obtain additional half-perimeter wirelength (HPWL) reduction. Experiments on the ISPD2005 benchmark show that C2FPlace reduces HPWL by 17.82\% over EGPlace and 17.86\% over RollPlace on average. On the ICCAD2025 benchmark, C2FPlace achieves the best average ranking among the compared methods under the evaluated power, performance, and area (PPA) metrics. Our codes are available in \href{https://github.com/lxxxxb/C2FPlace}{https://github.com/lxxxxb/C2FPlace}.

Problem

• Macro Placement
• Chip Physical Design
• Local Optima
• Layout Precision

Innovation

• Macro Placement
• Evolutionary Search
• Coarse-to-Fine Optimization
• Critical Macro Tuning
• Physical Design