Optimizing Energy Efficiency in Subthreshold RISC-V Cores

2025-02-10

AI Summary

Addressing the demand for ultra-low-power IoT applications operating in the subthreshold regime (300 mV), this work targets energy-efficient processor design at 130 nm. Method: We systematically evaluate and optimize multiple open-source RISC-V cores—SERV, QERV, PicoRV32, Ibex, Vex, and Rocket—through synthesis, physical implementation, and subthreshold timing modeling, leveraging a custom subthreshold standard-cell library; we particularly investigate the impact of buffer insertion on energy efficiency. Contribution/Results: We demonstrate, for the first time, that the two-stage pipelined Vex-2 achieves optimal performance–power trade-off in subthreshold operation—challenging the conventional assumption that deeper pipelines yield superior efficiency. We further identify buffer-related overhead as a fundamental energy-efficiency bottleneck in subthreshold designs. Quantitatively, Vex-2 delivers significantly higher performance than multi-cycle cores at comparable power, while consuming 23–37% less power than five-stage pipelined counterparts. It thus emerges as the most energy-efficient architecture, establishing a practical, implementable design paradigm for subthreshold processors.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV
• Intelligent Robots: Learning & Optimization for ROB

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Graph Algorithms and Modeling for the Web: Representation, reconstruction, and subgraph or motif discovery in Web-related graphs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Our goal in this paper is to understand how to maximize energy efficiency when designing standard-ISA processor cores for subthreshold operation. We hence develop a custom subthreshold library and use it to synthesize the open-source RISC-V cores SERV, QERV, PicoRV32, Ibex, Rocket, and two variants of Vex, targeting a supply voltage of 300 mV in a commercial 130 nm process. SERV, QERV, and PicoRV32 are multi-cycle architectures, while Ibex, Vex, and Rocket are pipelined architectures. We find that SERV, QERV, PicoRV32, and Vex are Pareto optimal in one or more of performance, power, and area. The 2-stage Vex (Vex-2) is the most energy efficient core overall, mainly because it uses fewer cycles per instruction than multi-cycle SERV, QERV, and PicoRV32 while retaining similar power consumption. Pipelining increases core area, and we observe that for subthreshold operation, the longer wires of pipelined designs require adding buffers to maintain a cycle time that is low enough to achieve high energy efficiency. These buffers limit the performance gains achievable by deeper pipelining because they result in cycle time no longer scaling proportionally with pipeline stages. The added buffers and the additional area required for pipelining logic however increase power consumption, and Vex-2 therefore provides similar performance and lower power consumption than the 5-stage cores Vex-5 and Rocket. A key contribution of this paper is therefore to demonstrate that limited-depth pipelined RISC-V designs hit the sweet spot in balancing performance and power consumption when optimizing for energy efficiency in subthreshold operation.

Problem

• Maximize energy efficiency in RISC-V cores
• Optimize subthreshold operation at 300 mV
• Balance performance and power in pipelined designs

Innovation

• Custom subthreshold library synthesis
• Pareto optimal RISC-V cores analysis
• Limited-depth pipelining enhances efficiency