Problem
Research questions and friction points this paper is trying to address.
High-bandwidth flash
memory wall
GPU memory systems
simulation
performance modeling
HBF-Sim: An Extensible HBF Simulator for Large-scale GPU Memory Systems
🤖 AI Summary
This study addresses the inability of existing simulators to accurately model address mapping, concurrent scheduling, and media management behaviors in High Bandwidth Flash (HBF)–GPU interactions. We propose the first GPU-integrated, end-to-end HBF simulation architecture that achieves closed-loop request path emulation by decoupling the controller from the memory stack. Specifically, we introduce an MSHR-based address mapping table to coalesce cache line requests and construct a page-level multi-stack parallel storage model to precisely characterize device queue and NAND flash behaviors. Experimental evaluations reveal performance bottlenecks induced by channel distribution constraints, offering critical guidance for next-generation HBF architecture design.
📝 Abstract
High-bandwidth flash (HBF) is introduced to address the memory wall, which can co-package a dense NAND stack with the GPU, targeting the performance gap between near-accelerator bandwidth and flash density. HBF, however, is neither a large HBM nor a fast NVMe SSD. Its usable bandwidth depends on how GPU cache-line requests map onto NAND pages, how concurrency spreads across channel-affine die sets, and how media management interacts with the GPU memory pipeline. To our knowledge, existing GPU, SSD, or HBF simulators cannot faithfully model this behavior. We present HBF-Sim, an extensible, reusable, and faithful HBF simulator integrated with simulated GPUs. It closes the loop between GPU issue limits, device queuing, and NAND behavior in one end-to-end request path. HBF-Sim separates a GPU-HBF interaction controller from page-based parallel stack storage, and it models the full GPU-HBF request path. It provides an MSHR-based address mapping table that merges cache-line requests into page-based operations, as well as a page-based multi-stack flash manager for highly parallel reads and writes. Validation tests and device-level microbenchmarks expose performance bottlenecks caused by limited channel distribution and resource conflicts, offering concrete guidance for next-generation HBF architectures.
Innovation
Methods, ideas, or system contributions that make the work stand out.
High-Bandwidth Flash (HBF)
GPU Memory Simulator
End-to-End Modeling
MSHR-based Address Mapping
Multi-stack Flash Manager
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