Circuit-tuning: A Mechanistic Approach for Identifying Parameter Redundancy and Fine-tuning Neural Networks

2025-02-10

AI Summary

This work addresses the challenge of interpreting neural network training dynamics. We propose “circuit-tuning”: first modeling node redundancy via intrinsic dimensionality to identify task-relevant computational circuits and mask redundant connections; then updating only critical parameters to reveal the self-organizing structural evolution during learning. This establishes the first interpretable, fine-grained framework for analyzing training dynamics, enabling task-directed structured sparse fine-tuning. Experiments demonstrate superior multi-task performance over standard fine-tuning, with a 72% average reduction in updated parameters while preserving generalization. The method further provides dynamic visual evidence of circuit evolution throughout training. Our core innovation unifies redundancy quantification and circuit-driven iterative optimization within an interpretable training analysis paradigm.

Technology Category

• Machine Learning: Probabilistic Circuits and Graphical Models
• Natural Language Processing: Learning & Optimization for NLP
• Search and Optimization: Learning to Search

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

The study of mechanistic interpretability aims to reverse-engineer a model to explain its behaviors. While recent studies have focused on the static mechanism of a certain behavior, the training dynamics inside a model remain to be explored. In this work, we develop an interpretable method for fine-tuning and reveal the mechanism behind learning. We first propose the concept of node redundancy as an extension of intrinsic dimension and explain the idea behind circuit discovery from a fresh view. Based on the theory, we propose circuit-tuning, a two-stage algorithm that iteratively performs circuit discovery to mask out irrelevant edges and updates the remaining parameters responsible for a specific task. Experiments show that our method not only improves performance on a wide range of tasks but is also scalable while preserving general capabilities. We visualize and analyze the circuits before, during, and after fine-tuning, providing new insights into the self-organization mechanism of a neural network in the learning process.

Problem

• Identify parameter redundancy in neural networks.
• Develop interpretable fine-tuning method for learning mechanisms.
• Explore self-organization in neural networks during fine-tuning.

Innovation

• Circuit-tuning for neural networks
• Node redundancy concept introduced
• Two-stage algorithm for fine-tuning