🤖 AI Summary
This study addresses the challenge that fragmented components within the quantum compilation stack hinder the co-optimization of fidelity, compilation time, and scheduling latency. To overcome this limitation, this work proposes a learning-based unified selector framework that integrates reinforcement learning, deep learning, and the MLIR infrastructure. For the first time, device selection, compilation optimization, and job scheduling are unified within a single architecture, enabling joint multi-objective optimization and dynamic adaptation to circuit characteristics and device states. By effectively bridging classical-quantum workflows, the proposed framework significantly enhances both compilation efficiency and execution fidelity for High-Performance Computing–Quantum Computing (HPCQC) infrastructures in the NISQ era.
📝 Abstract
High Performance Computing (HPC) and Quantum Computing (QC) systems are increasingly converging towards unified High Performance Computing-Quantum Computing (HPCQC) infrastructures, driven by a growing need to bridge classical and quantum workflows, which affects all levels of the system stack, from the hardware to compilers and runtimes, all the way to applications. However, today's QC devices are still in the Noisy Intermediate-Scale Quantum (NISQ) era, are error-prone and resource-limited, and therefore require specialized optimizations and topology mappings to achieve sufficient fidelity. This places special emphasis on proper compilation and optimization within the overall quantum software stack. Many existing stacks remain fragmented, with separate components responsible for device selection, compiler-pass optimization, and job queue scheduling. This paper proposes a unified, learning-based selector that integrates these disparate stages into a cohesive framework. Our proposed selector scheme leverages reinforcement learning and deep learning models that can be extended to simultaneously optimize multiple objectives -- such as fidelity, compilation time, and scheduling latency -- while dynamically adapting to circuit characteristics and device conditions.