Problem
Research questions and friction points this paper is trying to address.
Post-quantum cryptography
TCitH-based signatures
SLH-DSA alternatives
ASIC implementation
Resource-constrained platforms
Efficient TCitH-Based Alternatives to SLH-DSA: Cross-Layer ASIC Design of Mirath
🤖 AI Summary
This study addresses the high computational complexity and memory bottlenecks of TCitH-based signature schemes on embedded platforms by proposing a cross-layer hardware-software co-design methodology. Based on the RISC-V architecture, this work presents the first Mirath signature ASIC, fabricated and validated in a 22nm FD-SOI process. It achieves the inaugural hardware deployment of the TCitH scheme, confirming its viability as a non-lattice-based post-quantum cryptographic alternative. Experimental results demonstrate that, compared to the SLH-DSA standard, the proposed design reduces signing latency by 17.8× and chip area by 58%. This work establishes a new paradigm for efficient post-quantum signatures in resource-constrained scenarios.
📝 Abstract
To address the security risks posed by quantum computers, the U.S. National Institute of Standards and Technology (NIST) has standardized the post-quantum signature schemes ML-DSA, FN-DSA, and SLH-DSA. While ML-DSA and FN-DSA are lattice-based, SLH-DSA relies on hash-based assumptions. To support cryptographic agility against future vulnerabilities, NIST is evaluating non-lattice candidates as alternatives to SLH-DSA. Among these, TCitH-based schemes are particularly promising due to their compact keys and small signatures. However, their high computational complexity and memory footprint pose significant challenges for efficient implementations on resource-constrained embedded platforms. They remain largely unexplored in this context, particularly in ASIC implementations. To address this gap, we use a cross-layer methodology combining algorithmic and hardware layers to present, to the best of our knowledge, the first ASIC implementation of Mirath, a TCitH-based signature scheme, in a RISC-V-based system. The design is implemented in a 22nm FD-SOI technology node. Compared with an SLH-DSA ASIC implemented in the same technology node, the proposed architecture achieves 17.8x lower signing latency while requiring 58% less total cell area, showing the potential of TCitH-based signatures as efficient non-lattice alternatives from an implementation perspective.
Innovation
Methods, ideas, or system contributions that make the work stand out.
TCitH-based signature
Cross-layer ASIC design
Mirath
Post-quantum cryptography
RISC-V
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