Improved bounds for constant-power and low-power error-correcting cooling codes

2026-09-28

AI Summary

This study addresses the theoretical limits between power consumption and error-correction capability in cooling codes for on-chip buses by investigating the optimization of combinatorial bounds for binary CPECC and LPECC codes. Methodologically, the Zhao–Zhang upper bound condition is relaxed to w ≥ √2 t^(3/2), and rigorous analysis is conducted by integrating Steiner system constructions with combinatorial coding theory. The primary contribution lies in deriving a novel asymptotically tight upper bound for LPECCs and proving its asymptotic optimality. This new bound strictly improves upon existing results, significantly advancing the theoretical understanding of the performance limits of cooling codes.

Abstract

Low-power error-correcting cooling (LPECC) codes and constant-power error-correcting cooling (CPECC) codes provide error correction while controlling power consumption and thermal effects in on-chip buses. In this paper, we study binary CPECC and LPECC codes with \(e=w-3\). For CPECC codes, we extend the applicability of the upper bound previously obtained by Zhao and Zhang from the quadratic-order condition \(w\ge 2t(t+1)+2\) to \(w\ge w_0(t)\), where \(w_0(t)\sim \sqrt{2}\,t^{3/2}\). Using Steiner systems, we show that the CPECC bound is attainable and asymptotically tight for fixed \(t,w\). For LPECC codes, we establish the new upper bound \(\left\lfloor\frac{\binom{n+2}{3}}{\binom{w+t}{3}}\right\rfloor\) for \(w\ge \mu(t)\), where \(\mu(t)\sim \sqrt{2}\,t^{3/2}\). This bound is strictly smaller than the previous bound of Zhao and Zhang whenever both apply, and is asymptotically tight for fixed \(t,w\) in the stated range.

Problem

• error-correcting cooling codes
• constant-power
• low-power
• upper bounds
• on-chip buses

Innovation

• Error-correcting cooling codes
• Constant-power codes
• Low-power codes
• Steiner systems
• Upper bounds