The Vienna Architecture Description Language

2024-02-14

arXiv.org

AI Summary

To address the verbosity of processor architecture specifications and the redundancy in toolchain development, this paper introduces the Vienna Architecture Description Language (VADL)—a formal, high-level language tailored for processor specification. VADL pioneers a strict separation between instruction-set architecture (ISA) and microarchitecture (MiA) modeling, enabling full automation from a single formal specification: generation of compilers, assemblers, linkers, functional and cycle-accurate simulators, synthesizable HDL code, test suites, and documentation. Its open-source implementation, OpenVADL, enhances extensibility and engineering practicality over the original VADL. Empirical evaluation demonstrates that VADL specifications are concise and expressive; the generated tools are functionally complete and performant; and development and maintenance costs for compilers and simulators are significantly reduced. These results validate VADL’s expressive power, automation capability, and real-world engineering value.

Technology Category

• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems
• Search and Retrieval-Augmented AI: Vertical and domain-specific search

Abstract

The Vienna Architecture Description Language (VADL) is a powerful processor description language (PDL) that enables the concise formal specification of processor architectures. By utilizing a single VADL processor specification, the VADL system exhibits the capability to automatically generate a range of artifacts necessary for rapid design space exploration. These include assemblers, compilers, linkers, functional instruction set simulators, cycle-accurate instruction set simulators, synthesizable specifications in a hardware description language, as well as test cases and documentation. One distinctive feature of VADL lies in its separation of the instruction set architecture (ISA) specification and the microarchitecture (MiA) specification. This segregation allows users the flexibility to combine various ISAs with different MiAs, providing a versatile approach to processor design. In contrast to existing PDLs, VADL's MiA specification operates at a higher level of abstraction, enhancing the clarity and simplicity of the design process. Notably, with a single ISA specification, VADL streamlines compiler generation and maintenance by eliminating the need for intricate compiler-specific knowledge. The original VADL implementation has a restricted copyright. Therefore, the open source implementation OpenVADL was started. This article introduces VADL, compares the original VADL implementation with the ongoing OpenVADL implementation, describes the generator techniques in detail and demonstrates the power of the language and the performance of the generators in an empirical evaluation. The evaluation shows the expressiveness and conciseness of VADL and the efficiency of the generated artifacts.

Problem

• Formal specification of processor architectures
• Automatic generation of design artifacts
• Separation of ISA and microarchitecture specifications

Innovation

• Automated artifact generation
• Separates ISA and MiA
• High-level MiA abstraction