🤖 AI Summary
Traditional post-layout gate-level power analysis suffers from high computational overhead and poor scalability at sub-clock-cycle granularity, hindering its applicability to efficient power delivery network design and power side-channel security assessments. This work proposes PowerScope—the first machine learning–based framework for sub-cycle power estimation—that directly predicts high-fidelity power waveforms from RTL simulation traces without requiring repeated gate-level simulations. PowerScope establishes the first end-to-end mapping from RTL to sub-cycle power consumption, achieving significant efficiency gains: it attains an average absolute percentage error of 9% (median 5.88%) across diverse benchmarks and operates approximately 80× faster than commercial tools. The framework has been successfully applied to pre-silicon evaluation of power side-channel leakage.
📝 Abstract
Power estimation at sub-clock-cycle temporal resolutions is critical for tasks such as power delivery network (PDN) design, dynamic voltage droop analysis, and pre-silicon power side-channel security evaluation. Designers commonly rely on commercial post-layout gate-level power analysis tools for these tasks, but these flows are computationally expensive and scale poorly with design size and workload length. Machine learning (ML)-based power estimation frameworks have shown promise in accelerating power estimation, but prior efforts only address average power or per-cycle power estimation. We propose PowerScope, the first ML-based intra-cycle power estimation framework. PowerScope operates purely on RTL simulation traces at inference time, eliminating the need for post-layout gate-level simulation and power analysis per workload. Across a diverse benchmark suite, PowerScope achieves 5.88% median and 9% mean absolute percentage error compared to commercial post-layout gate-level power estimates while running ~80x faster. We further demonstrate that PowerScope's predictions can be reliably used for the downstream task of pre-silicon power side-channel leakage assessment.