🤖 AI Summary
This work addresses the degradation of logical symmetry in symmetric quantum circuits when compiled on constrained hardware, where uneven routing overhead induced by SWAP operations disrupts inherent symmetries. The authors demonstrate that this imbalance stems not from hardware limitations but from conventional compiler mapping strategies. To mitigate this issue, they propose a symmetry-aware qubit allocation method that enforces balanced routing. Evaluated on a 57-qubit heavy-hex architecture through exhaustive search, symmetry-preserving modeling, and error simulation, the approach achieves zero additional circuit depth for feasible patches while reducing symmetry-breaking by 92.7%. Experimental results further confirm its substantial superiority over general-purpose compilation optimizations in preserving circuit symmetry.
📝 Abstract
Mapping quantum programs to restricted physical chips requires SWAP operations, incurring depth and error penalties. In symmetric programs, this routing overhead breaks theoretical symmetry because identical logical roles experience unequal shuffling. While often attributed to hardware topology alone, we show this is a two-level phenomenon. A qubit patch's shape dictates if it can host a balanced assignment. When balance is possible, the actual imbalance is set by the logical-to-physical assignment, meaning a balanced assignment can distribute routing costs perfectly evenly at no extra depth. Through exhaustive search on a 57-qubit "heavy-hex" lattice, we prove these topological constraints. For a four-part ring, 108 of 124 connected patches admit a cost-free balanced assignment, with the 16 exceptions being star-shaped. For a six-part ring, cost-free balance is impossible on compact patches. For a fully connected four-part symmetry, balance is structurally impossible at any depth. Simulations using realistic error rates show that, relative to the worst-case concentrated assignment, balanced assignments reduce symmetry-breaking by 92.7% (95% CI [+89.8%, +95.3%]) for the raw metric and 87.0% (95% CI [+79.6%, +94.1%]) for the decoherence-corrected measure (p = 2.45 x 10^-32). Substrate error heterogeneity accounts for at most 10.8% of this effect. Notably, switching to the compiler's highest generic optimization level did not yield a statistically significant change in routing imbalance, highlighting the need for targeted symmetry-aware passes. When patch geometry permits, routing imbalance is a compiler choice rather than a hardware limitation. Thus, symmetry-aware assignment should be a primary objective for compiler optimization and chip design.