Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA

📅 2026-09-30
📈 Citations: 0
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🤖 AI Summary
This study addresses the joint optimization of routing and switch placement in chip design, a task governed by stringent physical constraints that challenge conventional solvers. To this end, we propose a first-of-its-kind validity-preserving hierarchical reinforcement learning framework that strictly confines the exploration space to feasible configurations via constructive operations. This approach integrates Gumbel Monte Carlo Tree Search for neural-guided optimization and introduces cross-layout pretraining to enhance generalization. By fundamentally circumventing invalid search trajectories, the proposed architecture significantly outperforms non-learning baselines. Furthermore, the pretraining initialization substantially improves both fine-tuning efficiency and solution quality on unseen instances.
📝 Abstract
Routing and switch placement are fundamental combinatorial optimization problems in chip design, requiring the joint optimization of routing topology and physical placement under strict structural, geometric and logical constraints. Existing approaches typically rely on carefully engineered heuristics that incorporate strong problem-specific biases to navigate the enormous space of possible designs. In this work, we introduce a hierarchical reinforcement learning framework for joint routing and switch placement at the level of logical communication routes. Starting from a minimal routing graph, our method progressively constructs increasingly expressive solutions through three coupled operations: switch expansion, switch placement, and route refinement. These operations preserve routing validity by construction, restricting exploration to feasible configurations where every communicating initiator-target pair has one assigned loop-free route. We explore the induced solution space using Gumbel Monte Carlo Tree Search, showing that neural-guided search substantially improves solution quality over non-learning optimization methods. Furthermore, pretraining across floorplans provides a strong initialization for fine-tuning on unseen instances.
Problem

Research questions and friction points this paper is trying to address.

routing
switch placement
combinatorial optimization
chip design
EDA
Innovation

Methods, ideas, or system contributions that make the work stand out.

Hierarchical Reinforcement Learning
Validity-Preserving
Gumbel Monte Carlo Tree Search
Joint Routing and Switch Placement
Pretraining
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