🤖 AI Summary
This work addresses the efficiency and flexibility limitations of general-purpose processor instruction sets when expressing complex or domain-specific computational tasks. The authors propose an FPGA soft-core architecture supporting runtime instruction reconfiguration, which embeds a reconfigurable region capable of dynamically loading custom instruction bitstreams from main memory. The key innovation lies in the design of the LUTstruction-based FPGA architecture, enabling low-latency, fine-to-coarse-grained instruction-level reconfiguration. The study fully validates the “FPGA-in-FPGA” instruction implementation paradigm, demonstrating that the proposed architecture achieves flexible instruction set extension and high-frequency execution without incurring significant clock frequency overhead. Experimental results confirm the efficacy of this approach in enhancing both programmability and performance for specialized computing workloads.
📝 Abstract
General-purpose processors feature a limited number of instructions based on an instruction set. They can be numerous, such as with vector extensions that include hundreds or thousands of instructions, but this comes at a cost; they are often unable to express arbitrary tasks efficiently. This paper explores the concept of having reconfigurable instructions by incorporating reconfigurable areas in a softcore. It follows a relatively-recently proposed computer architecture concept for seamlessly loading instruction implementation-carrying bitstreams from main memory. The resulting softcore is entirely evaluated on an FPGA, essentially having an FPGA-on-an-FPGA for the instruction implementations, with no notable operating frequency overhead. This is achieved with a custom FPGA architecture called LUTstruction, which is tailored towards low-latency for custom instructions and wide reconfiguration, as well as a soft implementation for the purposes of architectural exploration.