🤖 AI Summary
Programmable photonic integrated circuits (PICs) demand precise optical path-length matching for components such as microring resonators, Mach–Zehnder interferometers (MZIs), and true-time-delay lines—a challenge unaddressed by conventional shortest-path routing.
Method: We propose a length-matching routing algorithm based on enhanced best-first search. It introduces a monotonic heuristic function, a detour-margin-driven pin-ordering mechanism, and dynamic search-space pruning to model and satisfy stringent length constraints efficiently. The algorithm ensures routing completeness and computational efficiency in multi-port scenarios.
Results: Experiments on diverse benchmarks demonstrate substantial reductions in search space and runtime, while guaranteeing sub-micrometer length-matching accuracy. The method exhibits superior robustness and scalability across varying layout sizes, outperforming existing approaches in both precision and efficiency.
📝 Abstract
In the realm of programmable photonic integrated circuits (PICs), precise wire length control is crucial for the performance of on-chip programmable components such as optical ring resonators, Mach-Zehnder interferometers, and optical true time-delay lines. Unlike conventional routing algorithms that prioritize shortest-path solutions, these photonic components require exact-length routing to maintain the desired optical properties.
To address these challenges, this paper presents different length-matching routing strategies to find exact-length paths while balancing search space and runtime efficiently. We propose a novel admissible heuristic estimator and a pruning method, designed to enhance the accuracy and efficiency of the search process. The algorithms are derived from the Best-First search with modified evaluation functions. For two-pin length-matching routing, we formally prove that the proposed algorithms are complete under monotonic heuristics. For multi-pin length-matching challenges, we introduce a pin-ordering mechanism based on detour margins to reduce the likelihood of prematurely blocking feasible routes. Through evaluations on various length-matching benchmarks, we analyze runtime and heuristic performance, demonstrating the effectiveness of the proposed approaches across different layout scenarios.