A Near-Cache Architectural Framework for Cryptographic Computing

2025-09-27

AI Summary

Post-quantum cryptography (PQC) algorithms suffer from 3–9× larger public keys and signatures, causing severe cache bandwidth bottlenecks and substantial degradation in performance and energy efficiency. To address this, we propose a Compute-Near-Cache (CNC) architecture that integrates reconfigurable bitline compute arrays adjacent to SRAM caches, supporting virtual-address mapping and custom ISA extensions to enable data-localized computation; coupled with a tightly coordinated core–cache data path, CNC drastically reduces off-chip data movement. Unlike prior near-cache computing approaches—limited by system compatibility and external bandwidth constraints—CNC is the first to enable efficient PQC acceleration on general-purpose processors without architectural modification. Experimental results demonstrate that CNC achieves significant improvements in PQC execution efficiency and energy efficiency while maintaining full binary compatibility with x86 and ARM systems, effectively alleviating the cache bandwidth bottleneck.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Computer Vision: Learning & Optimization for CV

Application Category

• Security and Privacy: Applications of cryptography
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Recent advancements in post-quantum cryptographic algorithms have led to their standardization by the National Institute of Standards and Technology (NIST) to safeguard information security in the post-quantum era. These algorithms, however, employ public keys and signatures that are 3 to 9$ imes$ longer than those used in pre-quantum cryptography, resulting in significant performance and energy efficiency overheads. A critical bottleneck identified in our analysis is the cache bandwidth. This limitation motivates the adoption of on-chip in-/near-cache computing, a computing paradigm that offers high-performance, exceptional energy efficiency, and flexibility to accelerate post-quantum cryptographic algorithms. Our analysis of existing works reveals challenges in integrating in-/near-cache computing into modern computer systems and performance limitations due to external bandwidth limitation, highlighting the need for innovative solutions that can seamlessly integrate into existing systems without performance and energy efficiency issues. In this paper, we introduce a near-cache-slice computing paradigm with support of customization and virtual address, named Crypto-Near-Cache (CNC), designed to accelerate post-quantum cryptographic algorithms and other applications. By placing SRAM arrays with bitline computing capability near cache slices, high internal bandwidth and short data movement are achieved with native support of virtual addressing. An ISA extension to facilitate CNC is also proposed, with detailed discussion on the implementation aspects of the core/cache datapath.

Problem

• Accelerating post-quantum cryptographic algorithms with near-cache computing
• Overcoming cache bandwidth bottlenecks in modern computer systems
• Integrating near-cache architecture without performance and efficiency issues

Innovation

• Near-cache computing for cryptographic acceleration
• SRAM arrays with bitline computing near cache slices
• ISA extension for core/cache datapath implementation