CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing

2025-09-26

AI Summary

IoT devices face encryption performance bottlenecks and high energy consumption due to data movement overhead in MCU-based systems. This paper proposes CryptoSRAM, a compute-in-memory architecture that repurposes standard SRAM arrays—without requiring dedicated accelerators—to perform cryptographic operations in situ. By co-scheduling physical addressing and DMA, the SRAM is transformed into a massively parallel cryptographic processing unit, enabling efficient execution of AES and SHA3. Compared to pure software implementations, CryptoSRAM achieves up to 74× and 67× higher throughput for AES and SHA3, respectively; relative to state-of-the-art hardware accelerators, it delivers up to 6× higher AES throughput. Crucially, CryptoSRAM maintains full MCU compatibility while significantly reducing hardware overhead and improving energy efficiency. This work establishes a new paradigm for high-security, low-overhead cryptography tailored to resource-constrained IoT endpoints.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Application Domains: Internet of Things, Sensor Networks & Smart Cities

Application Category

• Security and Privacy: Applications of cryptography
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Secure communication is a critical requirement for Internet of Things (IoT) devices, which are often based on Microcontroller Units (MCUs). Current cryptographic solutions, which rely on software libraries or dedicated hardware accelerators, are fundamentally limited by the performance and energy costs of data movement between memory and processing units. This paper introduces CryptoSRAM, an in-SRAM computing architecture that performs cryptographic operations directly within the MCU's standard SRAM array. By repurposing the memory array into a massively parallel processing fabric, CryptoSRAM eliminates the data movement bottleneck. This approach is well-suited to MCUs, which utilize physical addressing and Direct Memory Access (DMA) to manage SRAM, allowing for seamless integration with minimal hardware overhead. Our analysis shows that for common cryptographic kernels, CryptoSRAM achieves throughput improvements of up to 74$ imes$ and 67$ imes$ for AES and SHA3, respectively, compared to a software implementation. Furthermore, our solution delivers up to 6$ imes$ higher throughput than existing hardware accelerators for AES. CryptoSRAM demonstrates a viable and efficient architecture for secure communication in next-generation IoT systems.

Problem

• Performing cryptographic operations on MCUs with high throughput
• Eliminating data movement bottleneck between memory and processing units
• Enabling secure communication for IoT devices via in-SRAM computing

Innovation

• Performs cryptographic operations directly within SRAM
• Eliminates data movement bottleneck via in-memory computing
• Repurposes SRAM into parallel processing fabric for MCUs