Investigations of multi-socket high core count RISC-V for HPC workloads

2025-02-14

AI Summary

RISC-V remains constrained in high-performance computing (HPC) due to performance bottlenecks in multi-socket systems, particularly under high-concurrency memory access. Method: This work presents the first systematic evaluation of cross-socket behavior on a dual-socket, 64-core RISC-V SG2042 processor under HPC workloads, using standard benchmarks—including SPEC CPU, HPL, and STREAM—to characterize memory bandwidth and latency. Contribution/Results: We discover that SG2042 exhibits strong cross-socket thread scalability, achieving near-linear performance scaling across most HPC scenarios in multi-socket configurations. Moreover, we quantitatively characterize its memory subsystem’s intrinsic limitations for the first time, demonstrating that multi-socket interconnects effectively alleviate single-die resource constraints. These findings indicate that a well-designed multi-socket RISC-V architecture possesses tangible potential for practical HPC deployment.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems
• Computer Vision: Multi-modal Vision

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Abstract

Whilst RISC-V has become popular in fields such as embedded computing, it is yet to find mainstream success in High Performance Computing (HPC). However, the 64-core RISC-V Sophon SG2042 is a potential game changer as it provides a commodity available CPU with much higher core count than existing technologies. In this work we benchmark the SG2042 CPU hosted in an experimental, dual-socket, system to explore the performance properties of the CPU when running a common HPC benchmark suite across sockets. Earlier benchmarks found that, on the Milk-V Pioneer workstation, whilst the SG2042 performs well for compute bound codes, it struggles when pressure is placed on the memory subsystem. The performance results reported here confirm that, even on a different system, these memory performance limitations are still present and hence inherent in the CPU. However, a multi-socket configuration does enable the CPU to scale to a larger number of threads which, in the main, delivers an improvement in performance and-so this is a realistic system configuration for the HPC community.

Problem

• Evaluating RISC-V for HPC workloads
• Assessing multi-socket RISC-V performance
• Identifying memory subsystem limitations in RISC-V

Innovation

• Multi-socket RISC-V system
• High core count CPU
• HPC benchmark performance