Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study

2025-02-14

AI Summary

This work addresses the challenges of manual effort, high cost, and lack of attack-based validation in cross-architecture assertion migration for RISC-V processor security verification. We propose a semantic-mapping- and architecture-aware automated assertion migration framework. Methodologically, it is the first systematic approach enabling security assertion migration across RISC-V designs, integrating LLM-driven hardware attack modeling with assertion coverage analysis to close the loop on assertion generation, transformation, and validity verification. Key contributions include: (1) the first RISC-V–specific cross-architecture security assertion migration solution; and (2) the first empirical validation using LLM-generated diverse hardware trojans. Evaluated on five critical security modules, our framework achieves near-100% assertion migration success rate, effectively detects multiple hardware trojan variants, and significantly reduces verification effort and time overhead.

Technology Category

• Machine Learning: Hardware-aware ML
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Computer Vision: Adversarial Attacks & Robustness

Application Category

• Security and Privacy: Large-scale security measurements
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

RISC-V is gaining popularity for its adaptability and cost-effectiveness in processor design. With the increasing adoption of RISC-V, the importance of implementing robust security verification has grown significantly. In the state of the art, various approaches have been developed to strengthen the security verification process. Among these methods, assertion-based security verification has proven to be a promising approach for ensuring that security features are effectively met. To this end, some approaches manually define security assertions for processor designs; however, these manual methods require significant time, cost, and human expertise. Consequently, recent approaches focus on translating pre-defined security assertions from one design to another. Nonetheless, these methods are not primarily centered on processor security, particularly RISC-V. Furthermore, many of these approaches have not been validated against real-world attacks, such as hardware Trojans. In this work, we introduce a methodology for translating security assertions across processors with different architectures, using RISC-V as a case study. Our approach reduces time and cost compared to developing security assertions manually from the outset. Our methodology was applied to five critical security modules with assertion translation achieving nearly 100% success across all modules. These results validate the efficacy of our approach and highlight its potential for enhancing security verification in modern processor designs. The effectiveness of the translated assertions was rigorously tested against hardware Trojans defined by large language models (LLMs), demonstrating their reliability in detecting security breaches.

Problem

• Translate security assertions across processor designs
• Automate RISC-V security verification process
• Validate assertions against hardware Trojan attacks

Innovation

• Automated security assertion translation
• RISC-V architecture case study
• Hardware Trojan detection validation