🤖 AI Summary
This work addresses two critical reliability bottlenecks hindering wafer-scale integration of carbon nanotube field-effect transistors (CNFETs): environmental drift (air instability) and negative bias temperature instability (NBTI). We propose a novel, synergistic approach combining silicon nitride (SiN)-based back-end-of-line (BEOL) passivation packaging with high-frequency, low-duty-cycle AC/pulsed gate driving. The SiN encapsulation reduces the median threshold voltage drift over 90 days by approximately 8×, while 10 MHz AC driving at 20% duty cycle extends NBTI lifetime by more than four orders of magnitude. Under severe stress conditions (125 °C, V<sub>GS,stress</sub> = −1.2 V), devices demonstrate robust long-term operational stability. Critically, the solution is fully compatible with standard BEOL fabrication processes—enabling, for the first time, practical monolithic integration of complex logic circuits, including RISC-V processor cores and SRAM arrays, using CNFET technology.
📝 Abstract
Back-end-of-line (BEOL) logic integration is emerging as a complementary scaling path to supplement front-end-of-line (FEOL) Silicon. Among various options for BEOL logic, Carbon Nanotube Field-Effect Transistors (CNFETs) have been integrated within commercial silicon foundries, and complex CNFET circuits (e.g., RISC-V core, SRAM arrays) have been demonstrated. However, there lacks comprehensive studies that analyze the ambient drift (i.e., air-stability) and reliability of CNFETs. Here, for the first time, we thoroughly characterize and demonstrate how to overcome ambient drift and negative bias temperature instability (NBTI) in CNFETs using the following techniques: (1) Silicon Nitride encapsulation to limit ambient atmosphere induced threshold voltage shift (~8x reduction of median VT shift over 90 days) and (2) AC/pulsed operation to significantly improve CNFET NBTI vs. DC operation across a wide frequency range (e.g., 20% duty cycle AC operation at 10 MHz could extend CNFET NBTI time-to-failure by>10000x vs. DC for a target VT shift tolerance<100 mV with gate stress bias VGS,stress = -1.2 V at 125 C).