CellE: Automated Standard Cell Library Extension via Equality Saturation

2026-03-13

AI Summary

This work proposes an automated standard cell library augmentation methodology based on equality saturation to enhance the quality of results (QoR) in very-large-scale integrated circuit design. By constructing an e-graph to cluster all functionally equivalent subcircuits within a mapped netlist, and integrating formal verification with an efficient pattern mining algorithm, the approach exhaustively explores the implementation space and selects area-optimal realizations. This is the first effort to combine equality saturation with formal methods for cell library extension, achieving significant improvements in both area and delay: when integrated into a commercial design flow, it reduces area by 15.41% on average (up to 23.64%) and decreases delay by 8.00% on average.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability
• Search and Optimization: Sampling/Simulation-based Search
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving

Application Category

• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Web Mining and Content Analysis: Robustness and generalizability of Web mining methods
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities.

Problem

• standard cell library extension
• Quality of Results
• functionally equivalent subcircuits
• VLSI design
• area optimization

Innovation

• equality saturation
• standard cell library extension
• e-graph
• VLSI design
• pattern mining