🤖 AI Summary
Addressing the challenge of training large-scale physics-informed neural networks (PINNs) on silicon photonic chips—hindered by the absence of on-chip photonic memory, large device footprints, and incompatibility with backpropagation—this work proposes the first photonic PINN training framework tailored for edge-deployable, real-time, low-power partial differential equation (PDE) solving. Our method eliminates backpropagation via a sparse-grid Stein derivative estimator for gradient-free training; employs tensor-train decomposition to enable dimensionality-reduced, zeroth-order optimization; and introduces a scalable photonic tensor kernel hardware architecture. Evaluated on both low- and high-dimensional PDE benchmarks, the framework demonstrates robust convergence. Circuit-level simulations show over 60% reduction in chip area, two orders-of-magnitude improvement in energy efficiency, and real-time latency—significantly advancing the feasibility of photonic acceleration for scientific machine learning at the edge.
📝 Abstract
Physics-informed neural networks (PINNs) have shown promise in solving partial differential equations (PDEs), with growing interest in their energy-efficient, real-time training on edge devices. Photonic computing offers a potential solution to achieve this goal because of its ultra-high operation speed. However, the lack of photonic memory and the large device sizes prevent training real-size PINNs on photonic chips. This paper proposes a completely back-propagation-free (BP-free) and highly salable framework for training real-size PINNs on silicon photonic platforms. Our approach involves three key innovations: (1) a sparse-grid Stein derivative estimator to avoid the BP in the loss evaluation of a PINN, (2) a dimension-reduced zeroth-order optimization via tensor-train decomposition to achieve better scalability and convergence in BP-free training, and (3) a scalable on-chip photonic PINN training accelerator design using photonic tensor cores. We validate our numerical methods on both low- and high-dimensional PDE benchmarks. Through circuit simulation based on real device parameters, we further demonstrate the significant performance benefit (e.g., real-time training, huge chip area reduction) of our photonic accelerator.