SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes

2026-07-23

AI Summary

This work addresses the challenge of design rule violation (DRV) correction in sub-2nm advanced technology nodes, where complex design rules, dense multi-layer interconnects, and foundry constraints render conventional repair methods ineffective. The authors propose a self-supervised approach that operates without real violation labels by serializing multi-layer layout geometries into structured text sequences. A self-supervised language model reconstructs masked patterns from back-end-of-line (BEOL) contextual information, while natural-language-encoded design rules and high-temperature sampling generate diverse, rule-compliant layout candidates. These candidates are validated via industrial-grade DRC and subsequently used to fine-tune a domain-adapted visual-language model (VLM) capable of rule-aware geometric reasoning for DRV repair. Evaluated on 100 real-world sub-2nm test cases, the method improves repair success rates by 12%–25% over existing intelligent solutions, achieving up to 97% success across critical violation types including spacing, width, enclosure, and color-aware spacing.

Abstract

As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, dense multi-layer routing geometries, and foundry-specific constraints. While Large Language Models (LLMs) have recently demonstrated strong capabilities in EDA scripting and documentation, their application to visual layout understanding remains largely unexplored: diagnosing DRC violations from layout imagery demands precise geometric reasoning and foundry-specific rule knowledge absent from general-purpose VLM training. We propose SCALE, a framework with a self-supervised layout-generation stage for local DRV fixing at advanced nodes. Multi-layer layout geometry is serialized into structured text, and a fine-tuned language model learns to reconstruct randomly masked polygons from surrounding BEOL context alone without violation labels. At inference, natural-language rule constraints and high-temperature sampling steer generation toward diverse, violation-prone layout variants validated by an industrial signoff DRC checker, producing DRC-annotated layout--violation pairs used to fine-tune a domain-adapted DRC-VLM. This VLM provides rule-aware geometric guidance for local DRV repair, boosting state-of-the-art agents' solve rates by +12--25% (up to 97%) on 100 real sub-2nm cases spanning enclosure, spacing, width, and color-spacing violations.

Problem

• design-rule violation
• place-and-route
• advanced nodes
• layout generation
• geometric reasoning

Innovation

• self-supervised layout generation
• design rule violation (DRV) fixing
• visual language model (VLM)
• multi-layer routing geometry
• natural-language rule constraints