🤖 AI Summary
To address time-varying accuracy degradation in analog in-memory computing (AiMC) hardware—caused by device non-idealities such as noise, drift, and aging—this work proposes LionHeart, a hierarchical mapping framework. Its core innovation is the first layer-granularity, time-varying non-ideality-aware dynamic mapping mechanism, enabling accuracy-constrained analog/digital co-scheduling and overcoming the adaptability limitations of conventional static mapping. LionHeart integrates circuit-level non-ideality modeling, inter-layer accuracy sensitivity analysis, a multi-objective optimization solver, and a cycle-accurate simulation platform. Evaluated across multiple DNN models and datasets, it achieves inference accuracy approaching floating-point baselines while reducing system execution time by 6.1× and improving energy efficiency by 6.3×, all while strictly satisfying user-specified accuracy thresholds.
📝 Abstract
When arranged in a crossbar configuration, resistive memory devices can be used to execute MVM, the most dominant operation of many ML algorithms, in constant time complexity. Nonetheless, when performing computations in the analog domain, novel challenges are introduced in terms of arithmetic precision and stochasticity, due to non-ideal circuit and device behaviour. Moreover, these non-idealities have a temporal dimension, resulting in a degrading application accuracy over time. Facing these challenges, we propose a novel framework, named LionHeart, to obtain hybrid analog-digital mappings to execute DL inference workloads using heterogeneous accelerators. The accuracy-constrained mappings derived by LionHeart showcase, across different DNNs and datasets, high accuracy and potential for speedup. The results of the full system simulations highlight run-time reductions and energy efficiency gains that exceed 6X, with a user-defined accuracy threshold with respect to a fully digital floating point implementation.