Capacity Gains in MIMO Systems with Few-Bit ADCs Using Nonlinear Analog Circuits

2022-12-12

AI Summary

To address the quantization rate loss induced by low-resolution analog-to-digital converters (ADCs) in millimeter-wave massive MIMO receivers, this paper proposes a novel hybrid-signal receiver architecture that integrates nonlinear analog preprocessing—specifically envelope detection and polynomial computation—prior to sampling and quantization, jointly optimizing analog beamforming and low-bit quantization. For the first time, it systematically characterizes, from an information-theoretic perspective, the achievable rate gain enabled by such nonlinear preprocessing, thereby surpassing the fundamental performance limits of conventional linear preprocessing. Circuit validation is implemented in 22 nm FDSOI and 65 nm bulk CMOS technologies: the proposed design reduces power consumption by an order of magnitude compared to fully digital solutions, while measured achievable rates approach the theoretical upper bound of ideal high-resolution ADCs, significantly mitigating spectral efficiency degradation caused by few-bit quantization.

Abstract

Analog to Digital Converters (ADCs) are a major contributor to the power consumption of multiple-input multiple-output (MIMO) receivers with large antenna arrays operating in the millimeter wave carrier frequencies. This is especially the case in large bandwidth communication systems, due to the sudden drop in energy-efficiency of ADCs as the sampling rate is increased above 100MHz. Two mitigating energy-efficient approaches which have received significant recent interest are i) to reduce the number of ADCs via analog and hybrid beamforming architectures, and ii) to reduce the resolution of the ADCs which in turn decreases power consumption. However, decreasing the number and resolution of ADCs leads to performance loss -- in terms of achievable rates -- due to increased quantization error. In this work, we study the application of practically implementable nonlinear analog operators such as envelope detectors and polynomial operators, prior to sampling and quantization at the ADCs, as a way to mitigate the aforementioned rate-loss. A receiver architecture consisting of linear analog combiners, nonlinear analog operators, and few-bit ADCs is designed. The fundamental information theoretic performance limits of the resulting communication system, in terms of achievable rates, are investigated under various assumptions on the set of implementable analog operators. Extensive numerical evaluations and simulations of the communication system are provided to compare the set of achievable rates under different architecture designs and parameters. Circuit simulations and measurement results, based on both 22 nm FDSOI CMOS technology and 65 nm Bulk CMOS transistor technologies, are provided to justify the power efficiency of the proposed receiver architecture deploying envelope detectors and polynomial operators.

Problem

• Reduce ADC power consumption
• Minimize quantization error impact
• Enhance MIMO receiver efficiency

Innovation

• Non-linear analog operators
• Few-bit ADCs
• Power efficiency evaluation