The Simulation Semantics of Synthesisable Verilog

2025-02-26

AI Summary

The Verilog standard lacks a mathematically formalized semantics for its synthesizable subset; existing formalizations are hampered by internal inconsistencies in the standard and misalignment with industrial practice, limiting their utility for execution and verification. Method: We develop the first executable, hardware-design-compatible formal semantics for synthesizable Verilog—systematically identifying and resolving multiple logical contradictions in the standard’s synthesis-related semantics. Our approach integrates formal modeling, implementation in an executable metalanguage, and visual semantic representation, validated via rigorous standard-consistency analysis. Contribution/Results: We present the first formal semantics that simultaneously ensures executability, verifiability, and industrial applicability. The model successfully simulates multiple industrial-scale hardware designs. Accompanying open-source tooling includes an executable implementation and an interactive visualization framework, establishing a foundational basis for formal verification, simulator development, and future standard evolution.

Technology Category

• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Cognitive Modeling & Cognitive Systems: Symbolic Representations
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Semantics and Knowledge: Methods, algorithms and applications for the development of semantic models, knowledge graphs and other forms of structured data models with machine-interpretable semantics
• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems

Abstract

Despite numerous previous formalisation projects targeting Verilog, the semantics of Verilog defined by the Verilog standard -- Verilog's simulation semantics -- has thus far eluded definitive mathematical formalisation. Previous projects on formalising the semantics have made good progress but no previous project provides a formalisation that can be used to execute or formally reason about real-world hardware designs. In this paper, we show that the reason for this is that the Verilog standard is inconsistent both with Verilog practice and itself. We pinpoint a series of problems in the Verilog standard that we have identified in how the standard defines the semantics of the subset of Verilog used to describe hardware designs, that is, the synthesisable subset of Verilog. We show how the most complete Verilog formalisation to date inherits these problems and how, after we repair these problems in an executable implementation of the formalisation, the repaired implementation can be used to execute real-world hardware designs. The existing formalisation together with the repairs hence constitute the first formalisation of Verilog's simulation semantics compatible with real-world hardware designs. Additionally, to make the results of this paper accessible to a wider (nonmathematical) audience, we provide a visual formalisation of Verilog's simulation semantics.

Problem

• Formalise Verilog's simulation semantics
• Identify inconsistencies in Verilog standard
• Enable execution of real-world hardware designs

Innovation

• Formalising Verilog's simulation semantics
• Identifying inconsistencies in Verilog standard
• Providing executable implementation for hardware designs