🤖 AI Summary
Memory hierarchy latency disparities in multicore architectures significantly degrade software transactional memory (STM) performance. Method: This paper systematically surveys prior work that leverages only runtime-collected STM metrics—namely, shared data access热度 and thread behavioral characteristics—to guide thread-data co-mapping, distinguishing itself from hardware-assisted or static-analysis-based approaches. It introduces the first purely runtime-driven, low-overhead, high-accuracy dynamic mapping paradigm, grounded in STM-aware affinity modeling, fine-grained runtime monitoring, and cache-coherence-aware optimization. Contribution/Results: The study identifies key performance bottlenecks and critical optimization dimensions, establishing a theoretical foundation and practical methodology for adaptive thread-data mapping and compiler-runtime co-optimization in STM systems.
📝 Abstract
In current microarchitectures, due to the complex memory hierarchies and different latencies on memory accesses, thread and data mapping are important issues to improve application performance. Software transactional memory (STM) is an abstraction used for thread synchronization, replacing the use of locks in parallel programming. Regarding thread and data mapping, STM presents new challenges and mapping opportunities, since (1) STM can use different conflict detection and resolution strategies, making the behavior of the application less predictable and; (2) the STM runtime has precise information about shared data and the intensity with each thread accesses them. These unique characteristics provide many opportunities for low-overhead, but precise statistics to guide mapping strategies for STM applications. The main objective of this paper is to survey the existing work about thread and data mapping that uses solely information gathered from the STM runtime to guide thread and data mapping decisions. We also discuss future research directions within this research area.